1. Field of the Invention
The present invention relates to a semiconductor device, in particular a semiconductor device having a plurality of test elements formed in an array on a semiconductor substrate.
2. Description of Related Art
In resent manufacturing processes of semiconductor devices in which the downscaling has been advanced, variations in the electrical characteristics of components are large, and therefore it is necessary to accurately measure the variations in the electrical characteristics of the components in order to improve the yields. Therefore, a lot of devices to be tested (DUT: Device Under Test) are formed on a semiconductor wafer.
For example, Japanese Unexamined Patent Application Publication No. 2001-044285 discloses, in FIG. 9, a DUT to measure the electrical characteristics of transistors formed on a semiconductor wafer. This DUT requires pads for four terminals, i.e., for a gate, a source, a drain, and a substrate. That is, an area needed for one DUT is very large, and the number of DUTs mounted on a limited area is small. Therefore, it is impossible to perform a sufficient number of measurements to cope with the downscaling.
To solve this problem, K. Y. Y. Doong et al, “Field-Configurable Test Structure Array (FC-TSA): Enabling design for monitor, model and manufacturability”, Proc. IEEE 2006 ICMTS, 2006, p. 98-103 discloses, in FIG. 1, a DUT array in which a lot of DUTs are arranged in an array to increase the mounting density of DUTs, and the target DUT to be measured are selectable. In this DUT array, an address is input in parallel, so that a lot of pads, i.e., the same number of pads as the number of the bits are required. Accordingly, S. Saxena et al., “Test Structures and Analysis Techniques for Estimation of the Impact of Layout on MOSFET Performance and Variability”, Proc. IEEE 2004 ICMTS, 200, p. 263-266 discloses, in FIG. 1, a structure in which only the clock is input and an internal address is generated by the clock, so that the number of pads are reduced. Note that other techniques to which the present patent application relates to include Japanese Unexamined Patent Application Publication No. 2007-103946 and J. Einfeld et al., “A New Test Circuit for the Matching Characterization of npn Bipolar Transistors”, Proc. IEEE 2004 ICMTS, 2004, p. 127-131.
FIG. 13 is a figure for illustrating a problem to be solved by the present invention. A semiconductor device shown in FIG. 13 includes an address signal generating portion 1, an X-switch 4, a Y-switch 5, and a DUT array 6. Similarly to Saxena, this semiconductor device generates an address signal from a clock signal CLK in the address signal generating portion 1. The X-switch 4 and the Y-switch 5 are controlled by this address signal so that a target DUT to be measured within the DUT array 6 can be designated.